1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including a memory cell array constituted by arranging plural memory cells in the directions of rows and columns, the memory cells each having a charge accumulation region formed between a channel region and a control gate via insulation films and a programming method of the memory cell array. More particularly, the present invention relates to a nonvolatile semiconductor memory device whose memory cell is capable of storing data of three or more values.
2. Description of the Related Art
Conventionally as the most general flash memory of this kind of the nonvolatile semiconductor memory device, for example, EPROM thin oxide (ETOX, registered trade mark of Intel Corp.) type flash memory has been available.
FIGS. 12A and 12B are a schematic sectional view of a memory cell transistor constituting a memory cell of an ETOX type flash memory and its equivalent circuit. As shown in FIGS. 12A and 12B, a floating gate 40, which acts as a charge accumulation region, is formed on a channel region 41 between a source 45 and a drain 46 via a tunnel oxide film 43 and further, a control gate 42 is formed via an interlayer insulation film 44.
The operation principle of this ETOX type flash memory cell will be described. When programming in the memory cell, a voltage Vpp (e.g., 9 V) is applied to the control gate, while a reference voltage Vss (e.g., 0 V) is applied to the source and a voltage Vdp (e.g., 5 V) is applied to the drain. Consequently, a large current flows through the channel region between the source and drain, so that hot electrons are generated in a portion having a high electric field in the vicinity of the drain and the electrons are injected into the floating gate, thereby the threshold voltage being raised. That is, it comes that a great number of electrons are injected into the floating gate as shown in FIG. 13B.
When erasing a programmed memory cell, voltages Vnn (e.g., −9 V) and Vpe (e.g., 6 V) are applied to the control gate and the source, respectively, and then, the threshold voltage is lowered by pulling out electrons in the vicinity of the source. That is, the number of electrons is smaller as shown in FIG. 13A as compared to the programmed state.
An actual flash memory is not of a single memory cell, but as shown in FIG. 2, a memory cell array is constituted by disposing a plurality of memory cells in the form of an array. The control gates of plural (n+1 in FIG. 2) flash memories are connected to word lines (WL0 to WLn) and the drains of plural (m+1 in FIG. 2) flash memories are connected to bit lines (BL0 to BLm). In case of FIG. 2, the memory cell array is constituted of (n+1)×(m+1) flash memories.
Because in the memory cell array constituted of plural memory cells, there can coexist plural memory cells each having a different threshold voltage, these threshold voltages have distributions of the same quantity as the memory cells.
These threshold voltage states are shown in FIG. 14. FIG. 14 shows the distribution of the threshold voltage of each memory cell in a memory cell array in which the aforementioned flash memory cells are arranged. The abscissa axis indicates the threshold voltage of a memory cell and the ordinate axis indicates the quantity of memory cells within the memory cell array having a threshold voltage. In FIG. 14, a distribution of 4.5 V or more (threshold voltage range) in threshold voltage indicates a memory cell in a programmed state and a distribution of less than 3 V (threshold voltage range) in threshold voltage indicates a memory cell in an erased state. If the threshold voltage of the flash memory cell belongs to any one of the two threshold voltage ranges shown in FIG. 14, apparently it is possible to distinguish the two memory states with a single flash memory cell.
To read out the memory state of such a memory cell, Vdr (e.g., 1 V) is applied to the drain and Vgr (e.g., 5 V) is applied to the control gate. For example, if the threshold voltage is in the erased state and within a low threshold voltage range, a current flows to the memory cell and it is determined that data is “1”. On the other hand, if the threshold voltage is in a program state and within a high threshold voltage range, no current flows to the memory cell and it is determined that data is “0”.
In the programming operation sequence of the ETOX type flash memory, as a reading step for verifying whether or not threshold voltage is changed to the requested threshold voltage range, that is, whether or not program is made successfully, Vgv (e.g., 5 V) is applied to the control gate while Vdv (e.g., 1 V) is applied to the drain so as to read out data and then, the programming verification is carried out by comparing this with a predetermined reference voltage.
In the ETOX type flash memory, a multi-valued memory, which is larger than a bit (two-value) can be achieved in a single memory cell by providing three regions or more of the threshold voltage ranges shown in FIG. 14. As the method for the multi-value of setting data of three values or more, an occasional programming method of executing programming and verification repeatedly from a low state in threshold voltage range to a higher state is generally adopted. This is described, for example, in one of the following documents. The first document is “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories” IEEE Journal of Solid-State Circuits, Vol 31, No. 4, April 1996. The second document is “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications” IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996. The third document is “40-mm2 3-V-Only 50-MHz 64-Mb 2-b/cell CHE NOR Flash Memory” IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, November 2000.
FIG. 4 shows an example of threshold voltage distribution in case where four regions are provided for the threshold voltage ranges. As shown in FIG. 4, 2-bit storage states “11”, “10”, “01”, “00” are allocated in order from the lowest level of the threshold voltage. The relation between the four threshold voltage ranges shown in FIG. 4 and the quantity of electrons injected into the floating gate of the flash memory cell is shown in FIG. 15.
As the quantity of electrons within the floating gate increases, the threshold voltage of the flash memory cell increases. That is, a state in which there are no electrons (few electrons) in the floating gate is a state in which the threshold voltage is lowest (memory state “11” here (data “11” in FIG. 4)) and the threshold voltage range of the memory cell is less than 3.0 V. A state in which a larger number of electrons are injected into the floating gate than the memory state “11” so that the threshold voltage range of the flash memory cell is 3.7 V to 4.2 V is assumed to be memory state “10” (data “10” in FIG. 4). A state in which a larger number of electrons are injected into the floating gate than the memory state “10”, so that the threshold voltage range of the flash memory is 4.7 V to 5.2 V is assumed to be memory state “01” (data “01” in FIG. 4). A state in which a larger number of electrons are injected into the floating gate than the memory state “01” so that the threshold voltage range is more than 5.7 V is assumed to be memory state “00” (data “00” in FIG. 4).
FIG. 16 is a flow diagram showing a conventional occasional programming sequence for a case of storing four-values into a single memory cell. FIG. 17 expresses an operation following the programming sequence shown in FIG. 16 in time series with the word line voltage and bit line voltage. The waveform of each rectangle in FIG. 17 represents the word line voltage and bit line voltage in both operations for programming and verification and, in FIGS. 16 and 17, like step numbers are attached to corresponding operation steps.
Assume that the threshold voltage in the initial state of the memory cell is within a threshold voltage range corresponding to the memory state “11”. Then, assume that the word line voltage for setting this memory cell in a threshold voltage range corresponding to the memory state “10” is Vg10, the word line voltage for setting in a threshold voltage range of the memory state “01” is Vg01 and the word line voltage for setting in a threshold voltage range of the memory state “00” is Vg00. Consequently, the relation among the respective word line voltages is Vg10<Vg01<Vg00. Assuming that the threshold voltage after the control gate of a memory cell is programmed with Vgp is Vt as described in the non-patent document 3, if the program is made by increasing a voltage to be applied to the control gate by only ΔVgp, the threshold voltage of the memory cell is increased by only ΔVgp. That is, to increase the threshold voltage of the memory cell, it is necessary to increase a voltage to be applied to the control gate by just the amount equal to the increase in the threshold voltage.
The conventional occasional programming sequence will be described with reference to FIG. 16. When programming the memory cell to memory state “00” under conditions in which the memory state “11” is an initial state of the memory cell (ST1), first, the word line voltage is set to Vg10 and a waiting time is held until the voltage is stabilized and then, a voltage pulse having a pulse width Wp (e.g., 1 μsec) is applied to the bit line at a voltage of an amplitude Vdp (e.g., 5 V) so as to program to the memory state “10” (ST2). Then, the word line voltage is changed over to a verification voltage Vgv and the bit line voltage is changed over to a verification voltage Vdv. After each voltage is stabilized, the memory state “10” is verified by reading operation (ST3). As a result of the verification, whether or not all the programmed memory cells reach a threshold voltage range corresponding to the memory state “10” is determined (ST4) and for a memory cell which does not reach, the word line voltage Vg10 at the programming time is increased by only ΔVg10 (ST5). The programming for applying the word line voltage and the bit line voltage pulse (ST2) and the verification (ST3) are executed again and steps ST2 to ST5 are repeated until the threshold voltages of all the memory cells reach a threshold voltage range corresponding to the memory state “10”. Referring to FIG. 17, up to this step corresponds to the “10” programming period.
After the threshold voltages of all the programming target memory cells reach a threshold voltage range corresponding to the memory state “10”, the word line voltage is changed over to Vg01 and after the word line voltage is stabilized, a voltage pulse of an amplitude Vdp is applied to the bit line by only a pulse width Wp so as to program to the memory state “01” (ST6). Subsequently, the word line voltage is changed over to a verification voltage Vgv and the bit line voltage is changed over to a verification voltage Vdv. After the respective voltages are stabilized, the memory state “01” is verified by a reading operation (ST7). Like the programming to the memory state “10”, until all the programming target memory cells reach a threshold voltage range corresponding to the memory state “01” (determined in ST8), the word line voltage is increased by ΔVg01 (ST9) and by increasing the word line voltage by ΔVg01 (ST9), programming for applying the word line voltage and bit line voltage pulse (ST6) and the verification (ST7) are repeated. Referring to FIG. 17, up to here corresponds to the “01” programming period.
After the threshold voltages of all the programming target memory cells reach a threshold voltage range corresponding to the memory state “01”, the word line voltage is changed over to Vg00 and after the word line voltage is stabilized, programming to the memory state “00” is made in the same manner as step ST6 (ST10). Subsequently, the word line voltage is changed over to the verification voltage Vgv and the bit line voltage is changed over to the verification voltage Vdv and after each voltage is stabilized, the memory state “00” is verified by the reading operation (ST1). Then, the word line voltage is increased (ST13) by ΔVg00 each until all the programming target memory cells reach a threshold voltage range corresponding to the memory state “00” (ST12). The programming for applying the word line voltage and the bit line voltage (ST10) and the verification (ST11) are repeated and if the threshold voltages of all the programming target memory cells reach a threshold voltage range corresponding to the memory state “00” (ST13), the programming is completed. Referring to FIG. 17, up to here corresponds to “00” programming period.
As described above, according to the conventional occasional programming sequence, a programming step (ST2 to ST5) for the memory state “10”, a programming step (ST6 to ST9) for the memory state “01” and a programming step (ST10 to ST13) for the memory state “00” exist until programming to the memory state “00” is completed. Each programming step is not completed until the threshold voltages of all the programming target memory cells reach a threshold voltage range corresponding to each memory state “10” but the procedure does not proceed to a next programming step. In the meantime, programming is not made to the memory state “00” in part of the programming target memory cell but if programming to the memory state “10” or the memory state “01” occurs, a programming step for the memory state “10” or a programming step for the memory state “10” and “01” is executed to a corresponding memory cell, while a time taken for the programming maximizes when programming to the memory state “00”.
If the conventional occasional programming sequence is adopted as a multi-value programming method of the ETOX type flash memory cell, when programming is made from a certain initial state to another memory state, if a different memory state exists in the middle thereof, a verification step is needed for programming into that intermediate memory state so as to complete the programming into the intermediate memory state by step. Consequently, the word line voltage and bit line voltage need to be changed over due to the intermediate verification step, so that a waiting time until these voltages are stabilized is prolonged and a programming time until the programming operation is completed is prolonged, which is an inconvenience to be solved. Further because the quantity of the verifications increases until a final programming is completed, the programming time is further prolonged.
For the memory cell array constituted of plural memory cells, it is necessary to narrow the threshold voltage range corresponding to each memory state in order to secure a sufficient margin at the reading time. Assuming that a countermeasure for setting the word line voltage at a programming time at a low level or narrowing the programming pulse width or any other measure is taken so as to control changes in the threshold voltage at the programming time, the quantities of the programming and verification increase and further the programming time is prolonged, which are problems to be solved.